The use of solder bumps on a chip carrier (or other member) to facilitate mounting or attachment to a circuit carrying substrate is well known in the art. However, the closeness or density of the solder bumps and their corresponding solder pads has been limited using conventional technologies due to problems in preventing the solder pads when a flowing together and electrically shorting the solder pads when a reflow solder process is used. The inability to provide a high density solder bumps and solder pads has frustrated attempts to provide super miniaturized integrated circuit (IC) mounting techniques that are reliable in a mass production environment. Moreover, high density super miniaturized mounting techniques present significant alignment difficulties even when automated or robotic assembly methods are employed. Accordingly, a need exists in the art to provide a high density pad grid array suitable for receiving a solder bumped member that avoids the difficulties of prior mounting methods.